The present invention relates generally to forming mask layouts in integrated circuit chips. In particular, the present invention provides a method, computer program product, and computer system for forming mask layouts in integrated circuit chips by using phase shapes for forming printing assist features in developing critical features.
Integrated circuit chips continue to be used in an increasing variety of electronic devices. Simultaneously, the trend in integrated circuit chips is to create greater functional capacity with smaller devices. As a result, forming mask layouts for integrated circuit chips requires that smaller critical features be used.
Integrated circuit chips may be formed by depositing various material layers of conductive material over a silicon wafer or other suitable base. Each of the material layers may be etched by various means such as lithography, ion etching and other methods for creating wires, vias, switches and any number of circuitry features. All methods for etching conductive material have limitations as the desired feature becomes smaller.
As lithography methods become more aggressive in creating smaller features, they become more limited by diffraction and other effects. Alternating phase shift masks (altPSM) have found increased usage in lithography for integrated circuit chips manufacture and elsewhere because they allow creation of smaller dimension features.
Mask layers may be utilized to create the patterns that various methods such as lithography utilize for creating circuitry features. To enable aggressive lithography, double patterning or double exposure methods may be used. Double patterning and double exposure methods both create two mask layers, each mask layer requiring less aggressive lithography methods in creating features and thus allowing smaller features to be created with accuracy.